An exemplary conventional lightly doped drain transistor structure, such as that depicted in FIG. 1, suffers severe short channel effect for deep sub-micron device generation due to the trade-off and limitations of shallow junctions and low silicided source-drain resistance. Junction leakage is also a concern for silicided junctions. One approach to solve this problem is the use of raised source/drain regions to provide a transistor having ultra-shallow junctions. A raised source/drain region provides a necessary thickness so that contact metal will not short to the substrate. If a source/drain is made too deep into the substrate, it extends into the channel area, shortening the channel.
In the construction of raised source/drain transistors, it is important to control diffusion associated with dopants used to create the shallow junctions of the transistor. Typically, a first implant stage is performed prior to the deposition of the raised source/drain region in order to form an electrical connection underneath a thick sidewall spacing insulator, thereby coupling the moat to the channel region. However, the subsequent step of depositing the raised source/drain region may cause the previously disposed dopant to further diffuse to such an extent that the operating characteristics of the device are changed.
One approach to providing raised source/drain regions is to create such regions with the selective epitaxial ("selective epi") technique. See for example, U.S. Pat. No. 4,998,150. In this technique, epitaxial silicon is selectively deposited in the specified source/drain areas. However, selective epi growth in the source/drain areas is not considered to be a currently manufacturable process due to the loss of selectivity caused by defects on the field areas.